According to Moore's Law, a size of a transistor gradually decreases, and when the size decreases to a nanometer scale, a serious short-channel effect is induced, resulting in performance deterioration of the transistor. Therefore, how to suppress the short-channel effect has become an important research topic in the art.
A gate-all-around technology can improve a gate control capability by using a gate-all-around transistor channel, and is a common solution to suppression of the short-channel effect. Generally, a semiconductor nanowire is suitable for being used in a gate-all-around transistor structure. A source region, a channel, and a drain region may be disposed on the nanowire, a gate dielectric layer is disposed on a surface of the nanowire, and a gate metal layer is disposed on a surface of the gate dielectric layer. In this way, the gate-all-around structure is formed. In addition, considering that the nanowire features a high parasitic resistance and a small on-state current, parallel processing may be performed on a plurality of nanowires to obtain a stronger current driving capability. However, parallel connection of the plurality of nanowires increases circuit design complexity and fabrication complexity. In addition, due to a relatively small diameter, the nanowire has a quite high aspect ratio and low mechanical stability.